The present invention relates to a sampling clock pulse generator and more particularly to a sampling clock pulse generator as a sampling clock recovery circuit of a receiving system in a character multiplex broadcasting system, for example.
In the recent character multiplex broadcasting system, a clock-run-in signal for synchronizing the sampling of data is sent preceding digital data. A receiver recovers a sampling clock signal exactly synchronized with the incoming clock-run-in signal. For recovering this, a sampling clock pulse recovery circuit is provided in this system.
A transmitter superposes a digital signal for character broadcasting on a part of the horizontal period during a vertical blanking period of a television signal. The receiver samples the digital signal, and stores the sampled ones in a frame memory. In this type of multiplex broadcasting system, a clock-run-in signal (a binary signal of 16 bits as 1010 . . . ) is located at the head of the digital signal for sampling synchronization. This signal is used as a reference phase signal for data sampling. The receiver recovers a sampling clock signal synchronized with the clock-run-in signal, and samples the digital data using the recovered sampling clock signal.
A conventional sampling clock pulse generating circuit will be described. A gate signal is input to a first terminal of the recovery circuit. This gate signal is generated in synchronism with specific phase portions of a clock-run-in signal to be given later. The signal is formed by delaying a horizontal sync signal, for example. A digital signal formed by slicing a picture detected video signal at a predetermined level, is applied to a second terminal of the sampling clock recovery circuit. A clock signal at a much higher frequency than that of a sampling clock signal to be recovered is applied to a third terminal. The gate signal and the clock-run-in signal are input to an AND circuit. The AND circuit generates a reset signal for application to a frequency dividing circuit. The clock signal is frequency divided by the frequency dividing circuit. The signal appears, as a sampling clock signal, at the output terminal of the sampling clock recovery circuit.
Actually, it is a rare case that the clock-run-in signal takes an ideal waveform. An actual clock-run-in signal suffers from noises and a change of the duty ratio, since it is adversely influenced when passing through the transmitter, the transmitting path, and the receiving system. If a gate signal arrives at the AND circuit when the AND circuit receives the portion of the clock-run-in signal suffering from noise or change of the duty ratio, a reset signal is generated at an inappropriate time. The reset signal inappropriately timed is used for resetting the frequency dividing circuit. As a result, the phase relation of the sampling clock signal generated by the frequency divider is disordered. For this reason, the conventional sampling clock recovery circuit frequently recovers an instable sampling clock signal.
In the above example, the clock-run-in signal and the succeeding data are related with each other in a synchronized manner. Accordingly, if a sampling clock signal recovered is exactly synchronized with the clock-run-in signal, the data can exactly be sampled. However, the sampling phase obtained on the basis of the clock-run-in signal is not necessarily appropriate to the sampling of the data since it consists of a series of successive spectrums, not a single sinusoidal wave and is influenced by the crowd delay characteristic in the transmission line. In other words, the frequency components of the data have different propagation times, respectively, possibly resulting in a waveform distortion of the data signal.
Thus, when the data is sampled at inappropriate phases, data can incorrectly be recognized.